LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;


ENTITY core_32_syn IS
generic
(
	cores : natural := 16
);
PORT
	(
		clk		           : IN STD_LOGIC;
		
		inst_ram_input  : in std_logic_vector(35 downto 0);
		inst_ram_addr   : in unsigned(6 downto 0);
		inst_ram_wren   : in std_logic_vector(cores-1 downto 0);
		
		data_ram_input  : in std_logic_vector(35 downto 0);
		data_ram_addr   : in unsigned(6 downto 0);
		data_ram_wren   : in std_logic_vector(cores-1 downto 0);
		
		reg_out 		: out std_logic_vector(cores-1 downto 0)	
	);
END core_32_syn;



ARCHITECTURE bhv OF core_32_syn IS
  
	signal reg_out_buffer : std_logic_vector((cores*32)-1 downto 0);	

	component core_32 IS
	PORT
	(
		clk		           : IN STD_LOGIC;
		
		inst_ram_input  : in std_logic_vector(35 downto 0);
		inst_ram_addr   : in unsigned(6 downto 0);
		inst_ram_wren   : in std_logic;
		
		data_ram_input  : in std_logic_vector(35 downto 0);
		data_ram_addr   : in unsigned(6 downto 0);
		data_ram_wren   : in std_logic;
		
		reg_out 		: out std_logic_vector(31 downto 0)	
	);
	END component;

BEGIN

	
	core : for i in 1 to cores generate
	design : core_32
	PORT map
	(
		clk		       => clk,	
		inst_ram_input  => inst_ram_input,
		inst_ram_addr   => inst_ram_addr,
		inst_ram_wren   => inst_ram_wren(i-1),
		data_ram_input  => data_ram_input,
		data_ram_addr   => data_ram_addr,
		data_ram_wren   => data_ram_wren(i-1),
		reg_out 		=> reg_out_buffer((i*32)-1 downto ((i-1)*32))
	);
	end generate core;

	process (reg_out_buffer) 
	begin
		for i in 1 to cores loop
			reg_out(i-1) <= reg_out_buffer((32*i)-i);
		end loop;
	end process;

END bhv;









